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r ds005 (v. 1.7) october 4, 1999 - product speci?cation 6-73 xc4000e and xc4000x series field programmable gate arrays 6 xc4000xl electrical speci?cations de?nition of terms in the following tables, some speci?cations may be designated as advance or preliminary. these terms are de?ned as follows: advance: initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device families. values are subject to change. use as estimates, not for production. preliminary: based on preliminary characterization. further changes are not expected. unmarked: speci?cations not identi?ed as either advance or preliminary are to be considered final. except for pin-to-pin input and output parameters, the a.c. parameter delay speci?cations included in this document are derived from measuring internal test patterns. all speci?cations are representative of worst-case supply voltage and junction temperature conditions. all speci?cations subject to change without notice. xc4000xl d.c. characteristics absolute maximum ratings recommended operating conditions description units v cc supply voltage relative to ground -0.5 to 4.0 v v in input voltage relative to ground (note 1) -0.5 to 5.5 v v ts voltage applied to 3-state output (note 1) -0.5 to 5.5 v v cct longest supply voltage rise time from 1 v to 3v 50 ms t stg storage temperature (ambient) -65 to +150 c t sol maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm) +260 c t j junction temperature ceramic packages +150 c plastic packages +125 c note 1: maximum dc excursion above v cc or below ground must be limited to either 0.5 v or 10 ma, whichever is easier to achieve. during transitions, the device pins may undershoot to -2.0 v or overshoot to v cc +2.0 v, provided this over or undershoot lasts less than 10 ns and with the forcing current being limited to 200 ma. note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under recommended operating conditions is not implied. exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. symbol description min max units v cc supply voltage relative to gnd, t j = 0 c to +85 c commercial 3.0 3.6 v supply voltage relative to gnd, t j = -40 c to +100 c industrial 3.0 3.6 v v ih high-level input voltage 50% of v cc 5.5 v v il low-level input voltage 0 30% of v cc v t in input signal transition time 250 ns notes: at junction temperatures above those listed above, all delay parameters increase by 0.35% per c. input and output measurement threshold is ~50% of v cc .
r xc4000e and xc4000x series field programmable gate arrays 6-74 ds005 (v. 1.7) october 4, 1999 - product speci?cation d.c. characteristics over recommended operating conditions power-on power supply requirements xilinx fpgas require a minimum rated power supply current capacity to insure proper initialization, and the power supply ramp-up time does affect the current required. a fast ramp-up time requires more current than a slow ramp-up time. the slowest ramp-up time is 50 ms. current capacity is not speci?ed for a ramp-up time faster than 2ms. the current capacity varies linearly with ramp-up time, e.g. , an xc4036xl with a ramp-up time of 25 ms would require a capacity predicted by the point on the straight line drawn from 1a at 120 m s to 500 ma at 50 ms at the 25 ms time mark. this point is approximately 750 ma . symbol description min max units v oh high-level output voltage @ i oh = -4.0 ma, v cc min (lvttl) 2.4 v high-level output voltage @ i oh = -500 m a, (lvcmos) 90% v cc v v ol low-level output voltage @ i ol = 12.0 ma, v cc min (lvttl) (note 1) 0.4 v low-level output voltage @ i ol = 1500 m a, (lvcmos) 10% v cc v v dr data retention supply voltage (below which configuration data may be lost) 2.5 v i cco quiescent fpga supply current (note 2) 5 ma i l input or output leakage current -10 +10 m a c in input capacitance (sample tested) bga, sbga, pq, hq, mq packages 10 pf pga packages 16 pf i rpu pad pull-up (when selected) @ v in = 0 v (sample tested) 0.02 0.25 ma i rpd pad pull-down (when selected) @ v in = 3.6 v (sample tested) 0.02 0.15 ma i rll horizontal longline pull-up (when selected) @ logic low 0.3 2.0 ma note 1: with up to 64 pins simultaneously sinking 12 ma. note 2: with no output current loads, no active input or longline pull-up resistors, all i/o pins tri-stated and ?oating. product description ramp-up time fast (120 m s) slow (50 ms) xc4005 - 36xl minimum required current supply 1 a 500 ma xc4044- 62xl minimum required current supply 2 a 500 ma xc4085xl minimum required current supply 2 a 1 500 ma notes: 1. the xc4085xl fast ramp-up time is 5 ms. devices are guaranteed to initialize properly with the minimum current listed above. a larger capacity power supply may result in a larger initialization current. this speci?cation applies to commercial and industrial grade products only. ramp-up time is measured from 0 v dc to 3.6 v dc . peak current required lasts less than 3 ms, and occurs near the internal power-on reset threshold voltage. after initialization and before con?guration, i cc max is less than 10 ma.
r ds005 (v. 1.7) october 4, 1999 - product speci?cation 6-75 xc4000e and xc4000x series field programmable gate arrays 6 xc4000xl a.c. characteristics testing of the switching parameters is modeled after testing methods speci?ed by mil-m-38510/605. all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. listed below are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb ?ip-?ops are clocked by the global clock net. when fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven from the same global clock, the delay is longer. for more speci?c, more precise, and worst-case guaranteed data, re?ecting the actual routing structure, use the values provided by the static timing analyzer (trce in the xilinx development system) and back-annotated to the simulation net list. these path delays, provided as a guideline, have been extracted from the static timing analyzer report. all timing parameters assume worst-case operating conditions (supply voltage and junction temperature. values apply to all xc4000xl devices and are expressed in nanoseconds unless otherwise noted. global low skew buffer to clock k speed grade all -3 -2 -1 -09 -08 units description symbol device min max max max max max delay from pad through gls buffer to any clock input, k t gls xc4002xl 0.3 2.1 1.8 1.6 1.5 ns xc4005xl 0.4 2.7 2.3 2.0 1.9 ns xc4010xl 0.5 3.2 2.8 2.4 2.3 ns xc4013xl 0.6 3.6 3.1 2.7 2.6 2.3 ns xc4020xl 0.7 4.0 3.5 3.0 2.9 ns xc4028xl 0.9 4.4 3.8 33 3.2 ns xc4036xl 1.1 4.8 4.2 3.6 3.5 3.1 ns xc4044xl 1.2 5.3 4.6 4.0 3.9 ns xc4052xl 1.3 5.7 5.0 4.5 4.4 ns xc4062xl 1.4 6.3 5.4 4.7 4.6 4.0 ns xc4085xl 1.6 7.2 6.2 5.7 5.5 ns
r xc4000e and xc4000x series field programmable gate arrays 6-76 ds005 (v. 1.7) october 4, 1999 - product speci?cation global early bufges 1, 2, 5, and 6 to iob clock global early bufges 3, 4, 7, and 8 to iob clock speed grade all -3 -2 -1 -09 -08 units description symbol device min max max max max max delay from pad through ge buffer to any iob clock input. t ge xc4002xl xc4005xl xc4010xl xc4013xl xc4020xl xc4028xl xc4036xl xc4044xl xc4052xl xc4062xl xc4085xl 0.1 0.3 0.3 0.4 0.4 0.3 0.3 0.2 0.3 0.3 0.4 1.6 1.9 2.2 2.4 2.6 2.8 3.1 3.5 4.0 4.9 5.8 1.4 1.8 1.9 2.1 2.2 2.4 2.7 3.0 3.5 4.3 5.1 1.3 1.7 1.7 1.8 2.1 2.1 2.3 2.6 3.0 3.7 4.7 1.2 1.6 1.7 1.7 2.0 2.0 2.2 2.4 3.0 3.4 4.3 1.5 1.9 3.0 ns ns ns ns ns ns ns ns ns ns ns speed grade all -3 -2 -1 -09 -08 units description symbol device min max max max max max delay from pad through ge buffer to any iob clock input. t ge xc4002xl xc4005xl xc4010xl xc4013xl xc4020xl xc4028xl xc4036xl xc4044xl xc4052xl xc4062xl xc4085xl 0.5 0.7 0.7 0.7 0.8 0.9 0.9 1.0 1.1 1.2 1.3 2.8 3.1 3.5 3.8 4.1 4.4 4.7 5.1 5.5 5.9 6.8 2.5 2.8 3.1 3.3 3.6 3.9 4.2 4.5 4.8 5.2 6.0 2.1 2.7 2.8 2.9 3.4 3.4 3.7 4.0 4.3 4.8 5.5 1.7 2.5 2.7 2.8 3.2 3.3 3.6 3.7 4.3 4.5 5.2 2.4 3.1 4.0 ns ns ns ns ns ns ns ns ns ns ns
r ds005 (v. 1.7) october 4, 1999 - product speci?cation 6-77 xc4000e and xc4000x series field programmable gate arrays 6 xc4000xl clb characteristics testing of switching parameters is modeled after testing methods speci?ed by mil-m-38510/605. all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. listed below are representative values. for more speci?c, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (trce in the xilinx development system) and back-annotated to the simulation net list. all timing parameters assume worst-case operating conditions (supply voltage and junction temperature). values apply to all xc4000xl devices and are expressed in nanoseconds unless otherwise noted. clb switching characteristic guidelines speed grade -3 -2 -1 -09 -08 description symbol min max min max min max min max min max combinatorial delays f/g inputs to x/y outputs f/g inputs via h to x/y outputs f/g inputs via transparent latch to q outputs c inputs via sr/h0 via h to x/y outputs c inputs via h1 via h to x/y outputs c inputs via din/h2 via h to x/y outputs c inputs via ec, din/h2 to yq, xq output (bypass) t ilo t iho t ito t hh0o t hh1o t hh2o t cbyp 1.6 2.7 2.9 2.5 2.4 2.5 1.5 1.5 2.4 2.6 2.2 2.1 2.2 1.3 1.3 2.2 2.2 2.0 1.9 2.0 1.1 1.2 2.0 2.0 1.8 1.6 1.8 1.0 1.1 1.9 1.8 1.8 1.5 1.8 0.9 clb fast carry logic operand inputs (f1, f2, g1, g4) to c out add/subtract input (f3) to c out initialization inputs (f1, f3) to c out c in through function generators to x/y outputs c in to c out , bypass function generators carry net delay, c out to c in t opcy t ascy t incy t sum t byp t net 2.7 3.3 2.0 2.8 0.26 0.32 2.3 2.9 1.8 2.6 0.23 0.28 2.0 2.5 1.5 2.4 0.20 0.25 1.6 1.8 1.0 1.7 0.14 0.24 1.6 1.8 0.9 1.5 0.14 0.24 sequential delays clock k to flip-flop outputs q clock k to latch outputs q t cko t cklo 2.1 2.1 1.9 1.9 1.6 1.6 1.5 1.5 1.4 1.4 setup time before clock k f/g inputs f/g inputs via h c inputs via h0 through h c inputs via h1 through h c inputs via h2 through h c inputs via din c inputs via ec c inputs via s/r, going low (inactive) cin input via f/g cin input via f/g and h t ick t ihck t hh0ck t hh1ck t hh2ck t dick t ecck t rck t cck t chck 1.1 2.2 2.0 1.9 2.0 0.9 1.0 0.6 2.3 3.4 1.0 1.9 1.7 1.6 1.7 0.8 0.9 0.5 2.1 3.0 0.9 1.7 1.6 1.4 1.6 0.7 0.8 0.5 1.9 2.7 0.8 1.6 1.4 1.2 1.4 0.6 0.7 0.4 1.3 2.1 0.8 1.5 1.4 1.1 1.4 0.6 0.7 0.4 1.2 2.0 hold time after clock k f/g inputs f/g inputs via h c inputs via sr/h0 through h c inputs via h1 through h c inputs via din/h2 through h c inputs via din/h2 c inputs via ec c inputs via sr, going low (inactive) t cki t ckih t ckhh0 t ckhh1 t ckhh2 t ckdi t ckec t ckr 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 clock clock high time clock low time t ch t cl 3.0 3.0 2.8 2.8 2.5 2.5 2.3 2.3 2.1 2.1 set/reset direct width (high) delay from c inputs via s/r, going high to q t rpw t rio 3.0 3.7 2.8 3.2 2.5 2.8 2.3 2.7 2.3 2.6 global set/reset minimum gsr pulse width t mrw 19.8 17.3 15.0 14.0 14.0 delay from gsr input to any q t mrq see table on page 85 for t rri values per device. toggle frequency (mhz) (for export control) f tog (mhz) 166 179 200 217 238
r xc4000e and xc4000x series field programmable gate arrays 6-78 ds005 (v. 1.7) october 4, 1999 - product speci?cation clb single-port ram synchronous (edge-triggered) write operation guidelines testing of switching parameters is modeled after testing methods speci?ed by mil-m-38510/605. all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. listed below are representative values. for more speci?c, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (trce in the xilinx development system) and back-annotated to the simulation net list. all timing parameters assume worst-case operating conditions (supply voltage and junction temperature). values apply to all xc4000xl devices and are expressed in nanoseconds unless otherwise noted. single port ram speed grade -3 -2 -1 -09 -08 size symbol min max min max min max min max min max write operation address write cycle time (clock k period) 16x2 32x1 t wcs t wcts 9.0 9.0 8.4 8.4 7.7 7.7 7.4 7.4 7.4 7.4 clock k pulse width (active edge) 16x2 32x1 t wps t wpts 4.5 4.5 4.2 4.2 3.9 3.9 3.7 3.7 3.7 3.7 address setup time before clock k 16x2 32x1 t ass t asts 2.2 2.2 2.0 2.0 1.7 1.7 1.7 1.7 1.6 1.7 address hold time after clock k 16x2 32x1 t ahs t ahts 0 0 0 0 0 0 0 0 0 0 din setup time before clock k 16x2 32x1 t dss t dsts 2.0 2.5 1.9 2.3 1.7 2.1 1.7 2.1 1.7 2.1 din hold time after clock k 16x2 32x1 t dhs t dhts 0 0 0 0 0 0 0 0 0 0 we setup time before clock k 16x2 32x1 t wss t wsts 2.0 1.8 1.8 1.7 1.6 1.5 1.6 1.5 1.6 1.5 we hold time after clock k 16x2 32x1 t whs t whts 0 0 0 0 0 0 0 0 0 0 data valid after clock k 16x2 32x1 t wos t wots 6.8 8.1 6.3 7.5 5.8 6.9 5.8 6.7 5.7 6.7 read operation address read cycle time 16x2 32x1 t rc t rct 4.5 6.5 3.1 5.5 2.6 3.8 2.6 3.8 2.6 3.8 data valid after address change (no write enable) 16x2 32x1 t ilo t iho 1.6 2.7 1.5 2.4 1.3 2.2 1.2 2.0 1.1 1.9 address setup time before clock k 16x2 32x1 t ick t ihck 1.1 2.2 1.0 1.9 0.9 1.7 0.8 1.6 0.8 1.5
r ds005 (v. 1.7) october 4, 1999 - product speci?cation 6-79 xc4000e and xc4000x series field programmable gate arrays 6 clb dual-port ram synchronous (edge-triggered) write operation guidelines testing of switching parameters is modeled after testing methods speci?ed by mil-m-38510/605. all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. listed below are representative values. for more speci?c, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (trce in the xilinx development system) and back-annotated to the simulation net list. all timing parameters assume worst-case operating conditions (supply voltage and junction temperature). values apply to all xc4000xl devices and are expressed in nanoseconds unless otherwise noted. clb ram synchronous (edge-triggered) write timing waveforms dual port ram speed grade -3 -2 --1 -09 -08 size symbol min max min max min max min max min max address write cycle time (clock k period) clock k pulse width (active edge) address setup time before clock k address hold time after clock k din setup time before clock k din hold time after clock k we setup time before clock k we hold time after clock k data valid after clock k 16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1 16x1 t wcds t wpds t asds t ahds t dsds t dhds t wsds t whds t wods 9.0 4.5 2.5 0 2.5 0 1.8 0 7.8 8.4 4.2 2.0 0 2.3 0 1.7 0 7.3 7.7 3.9 1.7 0 2.0 0 1.6 0 6.7 7.4 3.7 1.7 0 2.0 0 1.6 0 6.7 7.4 3.7 1.6 0 2.0 0 1.6 0 6.6 x6461 wclk (k) we address data in data out old new t dss t dhs t ass t ahs t wss t wps t whs t wos t ilo t ilo wclk (k) we address data in t dsds t dhds t asds t ahds t wsds t wpds t whds x6474 data out old new t wods t ilo t ilo single-port ram dual-port ram
r xc4000e and xc4000x series field programmable gate arrays 6-80 ds005 (v. 1.7) october 4, 1999 - product speci?cation xc4000xl pin-to-pin output parameter guidelines testing of switching parameters is modeled after testing methods speci?ed by mil-m-38510/605. all devices are 100% functionally tested. pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). listed below are representative values for typical pin locations and normal clock loading. for more speci?c, more precise, and worst-case guaranteed data, re?ecting the actual routing structure, use the values provided by the static timing analyzer (trce in the xilinx development system) and back-annotated to the simulation net list. these path delays, provided as a guideline, have been extracted from the static timing analyzer report. values are expressed in nanoseconds unless otherwise noted. output flip-flop, clock to out capacitive load factor figure 60 shows the relationship between i/o output delay and load capacitance. it allows a user to adjust the speci- ?ed output delay if the load capacitance is different than 50 pf. for example, if the actual load capacitance is 120 pf, add 2.5 ns to the speci?ed delay. if the load capac- itance is 20 pf, subtract 0.8 ns from the speci?ed output delay. figure 60 is usable over the speci?ed operating conditions of voltage and temperature and is independent of the out- put slew rate control. figure 60: delay factor at various capacitive loads speed grade all -3 -2 -1 -09 -08 units description symbol device min max max max max max global low skew clock to output us- ing output flip flop t ickof xc4002xl xc4005xl xc4010xl xc4013xl xc4020xl xc4028xl xc4036xl xc4044xl xc4052xl xc4062xl xc4085xl 1.2 1.3 1.4 1.5 1.6 1.8 2.0 2.1 2.2 2.3 2.5 7.1 7.7 8.2 8.6 9.0 9.4 9.8 10.3 10.7 11.3 12.2 6.1 6.6 7.1 7.4 7.8 8.1 8.5 8.9 9.3 9.7 10.5 5.4 5.8 6.2 6.5 6.8 7.1 7.4 7.8 8.3 8.5 9.5 5.1 5.4 5.8 6.1 6.4 6.7 7.0 7.4 7.9 8.1 9.0 5.6 6.4 7.3 ns ns ns ns ns ns ns ns ns ns ns for output slow option add t slow all devices 0.5 3.0 2.5 2.0 1.7 1.6 ns notes: clock-to-out minimum delay is measured with the fastest route and the lightest load, clock-to-out maximum delay is measured using the farthest distance and a reference load of one clock pin (ik or ok) per iob as well as driving all accessible clb ?ip-?ops. for designs with a smaller number of clock loads, the pad-to-iob clock pin delay as determined by the static timing analyzer (trce) can be added to the ac parameter tokpof and used as a worst-case pin-to-pin clock-to-out delay for clocked outputs for fast mode con?gurations. output timing is measured at ~50% v cc threshold with 50 pf external capacitive load. for different loads, see figure 1. x8257 -2 0 20406080 capacitance (pf) delta delay (ns) 100 120 140 -1 0 1 2 3
r ds005 (v. 1.7) october 4, 1999 - product speci?cation 6-81 xc4000e and xc4000x series field programmable gate arrays 6 output flip-flop, clock to out, bufge #s 1, 2, 5, and 6 output flip-flop, clock to out, bufge #s 3, 4, 7, and 8 speed grade all -3 -2 -1 -09 -08 units description symbol device min max max max max max global early clock to output using output flip flop. values are for buf- ge #s 1, 2, 5, and 6. t ickeof xc4002xl xc4005xl xc4010xl xc4013xl xc4020xl xc4028xl xc4036xl xc4044xl xc4052xl xc4062xl xc4085xl 1.0 1.2 1.2 1.3 1.3 1.2 1.2 1.1 1.2 1.2 1.3 6.6 6.9 7.2 7.4 7.6 7.8 8.1 8.5 9.0 9.9 10.8 5.7 6.1 6.2 6.4 6.5 6.7 7.0 7.3 7.8 8.6 9.4 5.1 5.5 5.5 5.6 5.9 5.9 6.1 6.4 6.8 7.5 8.5 4.8 5.2 5.3 5.3 5.6 5.6 5.8 6.0 6.6 7.0 7.9 4.8 5.2 6.3 ns ns ns ns ns ns ns ns ns ns ns notes: clock-to-out minimum delay is measured with the fastest route and the lightest load, clock-to-out maximum delay is measured using the farthest distance and a reference load of one clock pin (ik or ok) per iob as well as driving all accessible clb ?ip-?ops. for designs with a smaller number of clock loads, the pad-to-iob clock pin delay as determined by the static timing analyzer (trce) can be added to the ac parameter tokpof and used as a worst-case pin-to-pin clock-to-out delay for clocked outputs for fast mode con?gurations. output timing is measured at ~50% v cc threshold with 50 pf external capacitive load. for different loads, see figure 1. speed grade all -3 -2 -1 -09 -08 units description symbol device min max max max max max global early clock to output using output flip flop. values are for buf- ge #s 3, 4, 7, and 8. t ickeof xc4002xl xc4005xl xc4010xl xc4013xl xc4020xl xc4028xl xc4036xl xc4044xl xc4052xl xc4062xl xc4085xl 1.3 1.5 1.6 1.6 1.7 1.7 1.8 1.9 2.0 2.0 2.2 7.8 8.1 8.5 8.8 9.1 9.4 9.7 10.1 10.5 10.9 11.8 6.8 7.1 7.4 7.6 7.9 8.2 8.5 8.8 9.1 9.5 10.3 5.9 6.5 6.6 6.7 7.2 7.2 7.5 7.8 8.1 8.6 9.3 5.3 6.1 6.3 6.4 6.8 6.9 7.2 7.3 7.9 8.1 8.8 5.7 6.4 7.3 ns ns ns ns ns ns ns ns ns ns ns notes: clock-to-out minimum delay is measured with the fastest route and the lightest load, clock-to-out maximum delay is measured using the farthest distance and a reference load of one clock pin (ik or ok) per iob as well as driving all accessible clb ?ip-?ops. for designs with a smaller number of clock loads, the pad-to-iob clock pin delay as determined by the static timing analyzer (trce) can be added to the ac parameter tokpof and used as a worst-case pin-to-pin clock-to-out delay for clocked outputs for fast mode con?gurations. output timing is measured at ~50% v cc threshold with 50 pf external capacitive load. for different loads, see figure 1.
r xc4000e and xc4000x series field programmable gate arrays 6-82 ds005 (v. 1.7) october 4, 1999 - product speci?cation xc4000xl pin-to-pin input parameter guidelines testing of switching parameters is modeled after testing methods speci?ed by mil-m-38510/605. all devices are 100% functionally tested. pin-to-pin timing parameters are derived from measuring external and internal test patterns and are guaranteed over worst-case operating conditions (supply voltage and junction temperature). listed below are representative values for typical pin locations and normal clock loading. for more speci?c, more precise, and worst-case guaranteed data, re?ecting the actual routing structure, use the values provided by the static timing analyzer (trce in the xilinx development system) and back-annotated to the simulation net list. these path delays, provided as a guideline, have been extracted from the static timing analyzer report. values are expressed in nanoseconds unless otherwise noted global low skew clock, set-up and hold speed grade -3 -2 -1 -09 -08 units description symbol device min min min min min input setup and hold times no delay global low skew clock and iff global low skew clock and fcl t psn /t phn xc4002xl xc4005xl xc4010xl xc4013xl xc4020xl xc4028xl xc4036xl xc4044xl xc4052xl xc4062xl xc4085xl 2.5 / 1.5 1.2 / 2.6 1.2 / 3.0 1.2 / 3.2 1.2 / 3.7 1.2 / 4.4 1.2 / 5.5 1.2 / 5.8 1.2 / 7.1 1.2 / 7.0 1.2 / 9.4 2.2 / 1.3 1.1 / 2.2 1.1 / 2.6 1.1 / 2.8 1.1 / 3.2 1.1 / 3.8 1.1 / 4.8 1.1 / 5.0 1.1 / 6.2 1.1 / 6.1 1.1 / 8.2 1.9 / 1.2 0.9 / 2.0 0.9 / 2.3 0.9 / 2.4 0.9 / 2.8 0.9 / 3.3 0.9 / 4.1 0.9 / 4.4 0.9 / 5.4 0.9 / 5.3 0.9 / 7.1 1.7 / 1.0 0.8 / 1.7 0.8 / 2.0 0.8 / 2.1 0.8 / 2.4 0.8 / 2.9 0.8 / 3.6 0.8 / 3.8 0.8 / 4.7 0.8 / 4.6 0.8 / 6.2 0.8 / 2.1 0.8 / 3.6 0.8 / 4.6 ns ns ns ns ns ns ns ns ns ns ns partial delay global low skew clock and iff global low skew clock and fcl t psp /t php xc4002xl xc4005xl xc4010xl xc4013xl* xc4020xl xc4028xl xc4036xl* xc4044xl xc4052xl xc4062xl* xc4085xl 8.4 / 0.0 10. 5 / 0.0 11.1 / 0.0 6.1 / 1.0 11.9 / 1.0 12.3 / 1.0 6.4 / 1.0 13.1 / 1.0 11.9 / 1.0 6.7 / 1.2 12.9 / 1.2 7.3 / 0.0 9.1 / 0.0 9.7 / 0.0 5.3 / 1.0 10.3 / 1.0 10.7 / 1.0 5.6 / 1.0 11.4 / 1.0 10.3 / 1.0 5.8 / 1.2 11.2 / 1.2 6.3 / 0.0 7.9 / 0.0 8.4 / 0.0 4.6 / 1.0 9.0 / 1.0 9.3 / 1.0 4.8 / 1.0 9.9 / 1.0 9.0 / 1.0 5.1 / 1.2 9.8 / 1.2 5.5 / 0.0 6.9 / 0.0 7.3 / 0.0 4.0 / 1.0 7.8 / 1.0 8.1 / 1.0 4.2 / 1.0 8.6 / 1.0 7.8 / 1.0 4.4 / 1.2 8.5 / 1.2 3.7 / 0.5 4.0/ 0.8 4.2/ 1.0 ns ns ns ns ns ns ns ns ns ns ns full delay global low skew clock and iff t psd /t phd xc4002xl xc4005xl xc4010xl xc4013xl* xc4020xl xc4028xl xc4036xl* xc4044xl xc4052xl xc4062xl* xc4085xl 6.8 / 0.0 8.8 / 0.0 9.0 / 0.0 6.4 / 0.0 8.8 / 0.0 9.3 / 0.0 6.6 / 0.0 10.6 / 0.0 11.2 / 0.0 6.8 / 0.0 12.7 / 0.0 6.0 / 0.0 7.6 / 0.0 7.8 / 0.0 6.0 / 0.0 7.6 / 0.0 8.1 / 0.0 6.2 / 0.0 9.2 / 0.0 9.7 / 0.0 6.4 / 0.0 11.0 / 0.0 5.2 / 0.0 6.6 / 0.0 6.8 / 0.0 5.6 / 0.0 6.6 / 0.0 7.0 / 0.0 5.8 / 0.0 8.0 / 0.0 8.4 / 0.0 6.0 / 0.0 9.6 / 0.0 4.5 / 0.0 5.6 / 0.0 5.8 / 0.0 4.8 / 0.0 6.2 / 0.0 6.4 / 0.0 5.3 / 0.0 6.8 / 0.0 7.0 / 0.0 5.5 / 0.0 8.4 / 0.0 4.8 / 0.0 5.3 / 0.0 5.5 / 0.0 ns ns ns ns ns ns ns ns ns ns ns iff = input flip-flop or latch * the xc4013xl, xc4036xl, and 4062xl have signi?cantly faster partial and full delay setup times than other devices. notes: input setup time is measured with the fastest route and the lightest load. input hold time is measured using the furthest distance and a reference load of one clock pin per iob as well as driving all accessible clb ?ip-?ops. for designs with a smaller number of clock loads, the pad-to-iob clock pin delay as determined by the static timing analyzer (trce) can be used as a worst-case pin-to-pin no-delay input hold speci?cation.
r ds005 (v. 1.7) october 4, 1999 - product speci?cation 6-83 xc4000e and xc4000x series field programmable gate arrays 6 global early clock bufges 1, 2, 5, and 6 set-up and hold for iff and fcl speed grade -3 -2 -1 -09 -08 units description symbol device min min min min min input setup and hold times no delay global early clock and iff global early clock and fcl t psen /t phen t pfsen /t pfhen xc4002xl xc4005xl xc4010xl xc4013xl xc4020xl xc4028xl xc4036xl xc4044xl xc4052xl xc4062xl xc4085xl 2.8 / 1.5 1.2 / 4.1 1.2 / 4.4 1.2 / 4.7 1.2 / 4.6 1.2 / 5.3 1.2 / 6.7 1.2 / 6.5 1.2 / 6.7 1.2 / 8.4 1.2 / 8.7 2.5 / 1.3 1.1 / 3.6 1.1 / 3.8 1.1 / 4.1 1.1 / 4.0 1.1 / 4.6 1.1 / 5.8 1.1 / 5.7 1.1 / 5.8 1.1 / 7.3 1.1 / 7.5 2.2 / 1.2 0.9 / 3.1 0.9 / 3.3 0.9 / 3.6 0.9 / 3.5 0.9 / 4.0 0.9 / 5.1 0.9 / 4.9 0.9 / 5.1 0.9 / 6.3 0.9 / 6.6 1.9 / 1.0 0.8 / 2.7 0.8 / 2.9 0.8 / 3.1 0.8 / 3.0 0.8 / 3.5 0.8 / 4.4 0.8 / 4.3 0.8 / 4.4 0.8 / 5.5 0.8 / 5.7 0.5 / 2.7 0.5 / 3.7 0.5 / 4.7 ns ns ns ns ns ns ns ns ns ns ns partial delay global early clock and iff global early clock and fcl t psep /t phep t pfsep /t pfhep xc4002xl xc4005xl xc4010xl xc4013xl* xc4020xl xc4028xl xc4036xl* xc4044xl xc4052xl xc4062xl* xc4085xl 8.1 / 0.9 9.0 / 0.0 11.9 / 0.0 6.4 / 0.0 10.8 / 0.0 14.0 / 0.0 7.0 / 0.0 14.6 / 0.0 16.4 / 0.0 9.0 / 0.8 16.7 / 0.0 7.0 / 0.8 8.5 / 0.0 10.4 / 0.0 5.9 / 0.0 10.3 / 0.0 12.2 / 0.0 6.6 / 0.0 12.7 / 0.0 14.3 / 0.0 8.6 / 0.8 14.5 / 0.0 6.1 / 0.7 8.0 / 0.0 9.0 / 0.0 5.4 / 0.0 9.8 / 0.0 10.6 / 0.0 6.2 / 0.0 11.0 / 0.0 12.4 / 0.0 8.2 / 0.8 12.6 / 0.0 5.3 / 0.6 7.5 / 0.0 8.0 / 0.0 4.9 / 0.0 9.0 / 0.0 9.8 / 0.0 5.2 / 0.0 10.8 / 0.0 11.4 / 0.0 7.0 / 0.8 11.6 / 0.0 4.4 / 0.0 4.7 / 0.0 6.3 / 0.5 ns ns ns ns ns ns ns ns ns ns ns full delay global early clock and iff t psed /t phed xc4002xl xc4005xl xc4010xl xc4013xl* xc4020xl xc4028xl xc4036xl* xc4044xl xc4052xl xc4062xl* xc4085xl 6.7 / 0.0 10.8 / 0.0 10.3 / 0.0 10.0 / 0.0 12.0 / 0.0 12.6 / 0.0 12.2 / 0.0 13.8 / 0.0 14.1 / 0.0 13.1 / 0.0 17.9 / 0.0 5.8 / 0.0 9.4 / 0.0 9.0 / 0.0 8.7 / 0.0 10.4 / 0.0 11.0 / 0.0 10.6 / 0.0 12.0 / 0.0 12.3 / 0.0 11.4 / 0.0 15.6 / 0.0 5.1 / 0.0 8.2 / 0.0 7.8 / 0.0 7.6 / 0.0 9.1 / 0.0 9.5 / 0.0 9.2 / 0.0 10.5 / 0.0 10.7 / 0.0 9.9 / 0.0 13.6 / 0.0 4.4 / 0.0 7.1 / 0.0 6.8 / 0.0 6.6 / 0.0 7.9 / 0.0 8.3 / 0.0 8.0 / 0.0 9.1 / 0.0 9.3 / 0.0 8.6 / 0.0 11.8 / 0.0 6.0 / 0.0 7.2 / 0.0 7.8 / 0.0 ns ns ns ns ns ns ns ns ns ns ns iff = input flip-flop or latch, fcl = fast capture latch * the xc4013xl, xc4036xl, and 4062xl have signi?cantly faster partial and full delay setup times than other devices. notes: input setup time is measured with the fastest route and the lightest load. input hold time is measured using the furthest distance and a reference load of one clock pin per iob as well as driving all accessible clb ?ip-?ops. for designs with a smaller number of clock loads, the pad-to-iob clock pin delay as determined by the static timing analyzer (trce) can be used as a worst-case pin-to-pin no-delay input hold speci?cation.
r xc4000e and xc4000x series field programmable gate arrays 6-84 ds005 (v. 1.7) october 4, 1999 - product speci?cation global early clock bufges 3, 4, 7, and 8 set-up and hold for iff and fcl speed grade -3 -2 -1 -09 -08 units description symbol device min min min min min input setup & hold times no delay global early clock and iff global early clock and fcl t psen /t phen t pfsen /t pfhen xc4002xl xc4005xl xc4010xl xc4013xl xc4020xl xc4028xl xc4036xl xc4044xl xc4052xl xc4062xl xc4085xl 3.0 / 2.0 1.2 / 4.1 1.2 / 4.4 1.2 / 4.7 1.2 / 4.6 1.2 / 5.3 1.2 / 6.7 1.2 / 6.5 1.2 / 6.7 1.2 / 8.4 1.2 / 8.7 2.6 / 1.7 1.1 / 3.6 1.1 / 3.8 1.1 / 4.1 1.1 / 4.0 1.1 / 4.6 1.1 / 5.8 1.1 / 5.7 1.1 / 5.8 1.1 / 7.3 1.1 / 7.5 2.3 / 1.5 0.9 / 3.1 0.9 / 3.3 0.9 / 3.6 0.9 / 3.5 0.9 / 4.0 0.9 / 5.1 0.9 / 4.9 0.9 / 5.1 0.9 / 6.3 0.9 / 6.6 2.0 / 1.3 0.8 / 2.7 0.8 / 2.9 0.8 / 3.1 0.8 / 3.0 0.8 / 3.5 0.8 / 4.4 0.8 / 4.3 0.8 / 4.4 0.8 / 5.5 0.8 / 5.7 0.5 / 2.7 0.5 / 3.7 0.5 / 4.7 ns ns ns ns ns ns ns ns ns ns ns partial delay global early clock and iff global early clock and fcl t psep /t phep t pfsep /t pfhep xc4002xl xc4005xl xc4010xl xc4013xl* xc4020xl xc4028xl xc4036xl* xc4044xl xc4052xl xc4062xl* xc4085xl 7.3 / 1.5 8.4 / 0.0 10.3 / 0.0 5.4 / 0.0 9.8 / 0.0 12.7 / 0.0 6.4 / 0.8 13.8 / 0.0 14.5 / 0.0 8.4 / 1.5 14.5 / 0.0 6.4 / 1.3 7.9 / 0.0 9.0 / 0.0 4.9 / 0.0 9.3 / 0.0 11.0 / 0.0 5.9 / 0.8 12.0 / 0.0 12.7 / 0.0 7.9 / 1.5 12.7 / 0.0 5.5 / 1.2 7.4 / 0.0 7.8 / 0.0 4.4 / 0.0 8.8 / 0.0 9.6 / 0.0 5.4 / 0.8 10.4 / 0.0 11.0 / 0.0 7.4 / 1.5 11.0 / 0.0 4.8 / 1.0 7.2 / 0.0 7.4 / 0.0 4.3 / 0.0 8.5 / 0.0 9.3 / 0.0 5.0 / 0.8 10.2 / 0.0 10.7 / 0.0 6.8 / 1.5 10.8 / 0.0 4.0 / 0.0 4.6 / 0.2 6.2 / 0.0 ns ns ns ns ns ns ns ns ns ns ns full delay global early clock and iff t psed /t phed xc4002xl xc4005xl xc4010xl xc4013xl* xc4020xl xc4028xl xc4036xl* xc4044xl xc4052xl xc4062xl* xc4085xl 5.9 / 0.0 10.8 / 0.0 10.3 / 0.0 10.0 / 0.0 12.0 / 0.0 12.6 / 0.0 12.2 / 0.0 13.8 / 0.0 14.1 / 0.0 13.1 / 0.0 17.9 / 0.0 5.2 / 0.0 9.4 / 0.0 9.0 / 0.0 8.7 / 0.0 10.4 / 0.0 11.0 / 0.0 10.6 / 0.0 12.0 / 0.0 12.3 / 0.0 11.4 / 0.0 15.6 / 0.0 4.5 / 0.0 8.2 / 0.0 7.8 / 0.0 7.6 / 0.0 9.1 / 0.0 9.5 / 0.0 9.2 / 0.0 10.5 / 0.0 10.7 / 0.0 9.9 / 0.0 13.6 / 0.0 3.9 / 0.0 7.1 / 0.0 6.8 / 0.0 6.6 / 0.0 7.9 / 0.0 8.3 / 0.0 8.0 / 0.0 9.1 / 0.0 9.3 / 0.0 8.6 / 0.0 11.8 / 0.0 6.0 / 0.0 7.2 / 0.0 7.8 / 0.0 ns ns ns ns ns ns ns ns ns ns ns * the xc4013xl, xc4036xl, and 4062xl have signi?cantly faster partial and full delay setup times than other devices. iff = input flip flop or latch. fcl = fast capture latch notes: input setup time is measured with the fastest route and the lightest load. input hold time is measured using the furthest distance and a reference load of one clock pin per iob as well as driving all accessible clb ?ip-?ops. for designs with a smaller number of clock loads, the pad-to-iob clock pin delay as determined by the static timing analyzer (trce) can be used as a worst-case pin-to-pin no-delay input hold speci?cation.
r ds005 (v. 1.7) october 4, 1999 - product speci?cation 6-85 xc4000e and xc4000x series field programmable gate arrays 6 xc4000xl iob input switching characteristic guidelines testing of switching parameters is modeled after testing methods speci?ed by mil-m-38510/605. all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. listed below are representative values. for more speci?c, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer (trce in the xilinx development system) and back-annotated to the simulation net list. these path delays, provided as a guideline, have been extracted from the static timing analyzer report. all timing parameters assume worst-case operating conditions (supply voltage and junction temperature) . speed grade -3 -2 -1 -09 -08 units description symbol device min min min min min clocks clock enable (ec) to clock (ik) t ecik all devices 0.1 0.1 0.1 0.1 0.1 ns delay from fcl enable (ok) active edge to iff clock (ik) active edge t okik xc4002xl xc4013, 36, 62xl balance of family 3.0 2.2 2.2 2.7 1.9 1.9 2.3 1.6 1.6 2.3 1.6 1.6 1.6 ns ns ns setup times pad to clock (ik), no delay t pick xc4002xl xc4013, 36, 62xl balance of family 2.6 1.7 1.7 2.3 1.5 1.5 2.0 1.3 1.3 2.0 1.3 1.3 1.2 ns ns ns pad to clock (ik), via transparent fast cap- ture latch, no delay t pickf xc4002xl xc4013, 36, 62xl balance of family 3.2 2.3 2.3 2.9 2.0 2.0 2.5 1.8 1.8 2.4 1.7 1.7 1.6 ns ns ns pad to fast capture latch enable (ok), no delay t pock xc4013, 36, 62xl balance of family 1.2 1.2 1.0 1.0 0.9 0.9 0.9 0.9 0.9 ns ns hold times all hold times all devices 0 0 0 0 0 global set/reset minimum gsr pulse width t mrw all devices 19.8 17.3 15.0 14.0 14.0 ns global set/reset max max max max max delay from gsr input to any q t rri* xc4002xl xc4005xl xc4010xl xc4013xl xc4020xl xc4028xl xc4036xl xc4044xl xc4052xl xc4062xl xc4085xl 9.8 11.3 13.9 15.9 18.6 20.5 22.5 25.1 27.2 29.1 34.4 8.5 9.8 12.1 13.8 16.1 17.9 19.6 21.9 23.6 25.3 29.9 7.4 8.5 10.5 12.0 14.0 15.5 17.0 19.0 20.5 22.0 26.0 7.0 8.1 10.0 11.4 13.3 14.3 16.2 18.1 19.5 20.9 24.7 10.9 16.2 20.4 ns ns ns ns ns ns ns ns ns ns ns propagation delays pad to i1, i2 t pid all devices 1.6 1.4 1.2 1.1 1.0 ns pad to i1, i2 via transparent input latch, no delay t pli xc4002xl xc4013, 36, 62xl balance of family 4.7 3.1 3.1 4.2 2.7 2.7 3.6 2.4 2.4 3.5 2.2 2.2 2.1 ns ns ns pad to i1, i2 via transparent fcl and in- put latch, no delay t pfli x4002xl xc4013, 36, 62xl balance of family 5.4 3.7 3.7 4.7 3.3 3.3 4.1 2.8 2.8 3.9 2.7 2.7 2.5 ns ns ns clock (ik) to i1, i2 (flip-flop) clock (ik) to i1, i2 (latch enable, active low) fcl enable (ok) active edge to i1, i2 (via transparent standard input latch) t ikri t ikli t okli all devices all devices xc4002xl xc4013, 36, 62xl balance of family 1.7 1.8 5.2 3.6 3.6 1.5 1.6 4.6 3.1 3.1 1.3 1.4 4.0 2.7 2.7 1.2 1.3 3.8 2.6 2.6 1.2 1.3 2.5 ns ns ns ns ns iff = input flip-flop or latch, fcl = fast capture latch * indicates minimum amount of time to assure valid data.
r xc4000e and xc4000x series field programmable gate arrays 6-86 ds005 (v. 1.7) october 4, 1999 - product speci?cation revision control version nature of changes 2/1/99 (1.5) release included in the 1999 data book, section 6 5/14/99 (1.6) replaced electrical specification and pinout pages for e, ex, and xl families with separate updates and added url link on placeholder page for electrical specifications/pinouts for weblinx users 10/4/99 (1.7) added power-on specification.

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